Reversible machine code and its abstract processor architecture

Holger Bock Axelsen; Robert Glück; Tetsuo Yokoyama

doi:10.1007/978-3-540-74510-5_9

Reversible machine code and its abstract processor architecture

Holger Bock Axelsen, Robert Glück, Tetsuo Yokoyama

Department of Computer Science

41 Citations (Scopus)

Abstract

A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper.

Original language	English
Title of host publication	Computer Science - Theory and Applications : Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings
Editors	Volker Diekert, Mikhail Volkov, Andrei Voronkov
Publisher	Springer
Publication date	2007
Pages	56-69
ISBN (Print)	978-3-540-74509-9
DOIs	https://doi.org/10.1007/978-3-540-74510-5_9
Publication status	Published - 2007
Event	International Symposium on Computer Science in Russia - Ekaterinburg, Russian Federation Duration: 3 Sept 2007 → 7 Sept 2007 Conference number: 1

Conference

Conference	International Symposium on Computer Science in Russia
Number	1
Country/Territory	Russian Federation
City	Ekaterinburg
Period	03/09/2007 → 07/09/2007

Series	Lecture notes in computer science
Number	4649
ISSN	0302-9743

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10.1007/978-3-540-74510-5_9

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Axelsen, H. B., Glück, R., & Yokoyama, T. (2007). Reversible machine code and its abstract processor architecture. In V. Diekert, M. Volkov, & A. Voronkov (Eds.), Computer Science - Theory and Applications: Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings (pp. 56-69). Springer. https://doi.org/10.1007/978-3-540-74510-5_9

Reversible machine code and its abstract processor architecture. / Axelsen, Holger Bock; Glück, Robert; Yokoyama, Tetsuo.
Computer Science - Theory and Applications: Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings. ed. / Volker Diekert; Mikhail Volkov; Andrei Voronkov. Springer, 2007. p. 56-69 (Lecture notes in computer science; No. 4649).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Axelsen, HB, Glück, R & Yokoyama, T 2007, Reversible machine code and its abstract processor architecture. in V Diekert, M Volkov & A Voronkov (eds), Computer Science - Theory and Applications: Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings. Springer, Lecture notes in computer science, no. 4649, pp. 56-69, International Symposium on Computer Science in Russia, Ekaterinburg, Russian Federation, 03/09/2007. https://doi.org/10.1007/978-3-540-74510-5_9

Axelsen HB, Glück R, Yokoyama T. Reversible machine code and its abstract processor architecture. In Diekert V, Volkov M, Voronkov A, editors, Computer Science - Theory and Applications: Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings. Springer. 2007. p. 56-69. (Lecture notes in computer science; No. 4649). doi: 10.1007/978-3-540-74510-5_9

Axelsen, Holger Bock ; Glück, Robert ; Yokoyama, Tetsuo. / Reversible machine code and its abstract processor architecture. Computer Science - Theory and Applications: Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings. editor / Volker Diekert ; Mikhail Volkov ; Andrei Voronkov. Springer, 2007. pp. 56-69 (Lecture notes in computer science; No. 4649).

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Reversible machine code and its abstract processor architecture

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