Reversible machine code and its abstract processor architecture

TY - GEN

T1 - Reversible machine code and its abstract processor architecture

AU - Axelsen, Holger Bock

AU - Glück, Robert

AU - Yokoyama, Tetsuo

N1 - Conference code: 1

PY - 2007

Y1 - 2007

N2 - A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper.

AB - A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper.

U2 - 10.1007/978-3-540-74510-5_9

DO - 10.1007/978-3-540-74510-5_9

M3 - Article in proceedings

SN - 978-3-540-74509-9

T3 - Lecture notes in computer science

SP - 56

EP - 69

BT - Computer Science - Theory and Applications

A2 - Diekert, Volker

A2 - Volkov, Mikhail

A2 - Voronkov, Andrei

PB - Springer

T2 - International Symposium on Computer Science in Russia

Y2 - 3 September 2007 through 7 September 2007

ER -