A reversible processor architecture and its reversible logic design

Michael Kirkedal Thomsen; Holger Bock Axelsen; Robert Glück

doi:10.1007/978-3-642-29517-1_3

A reversible processor architecture and its reversible logic design

Michael Kirkedal Thomsen, Holger Bock Axelsen, Robert Glück

Department of Computer Science

14 Citations (Scopus)

Abstract

We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.

All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.

Original language	English
Title of host publication	Reversible Computation : Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers
Editors	Alexis De Vos, Robert Wille
Number of pages	13
Publisher	Springer
Publication date	2012
Pages	30-42
ISBN (Print)	978-3-642-29516-4
ISBN (Electronic)	978-3-642-29517-1
DOIs	https://doi.org/10.1007/978-3-642-29517-1_3
Publication status	Published - 2012
Event	3rd International Workshop on Reversible Computation - Gent, Belgium Duration: 4 Jul 2011 → 5 Jul 2011 Conference number: 3

Conference

Conference	3rd International Workshop on Reversible Computation
Number	3
Country/Territory	Belgium
City	Gent
Period	04/07/2011 → 05/07/2011

Series	Lecture notes in computer science
Volume	7165
ISSN	0302-9743

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10.1007/978-3-642-29517-1_3

Cite this

A reversible processor architecture and its reversible logic design. / Thomsen, Michael Kirkedal; Axelsen, Holger Bock; Glück, Robert.
Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. ed. / Alexis De Vos; Robert Wille. Springer, 2012. p. 30-42 (Lecture notes in computer science, Vol. 7165).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Thomsen, MK, Axelsen, HB & Glück, R 2012, A reversible processor architecture and its reversible logic design. in A De Vos & R Wille (eds), Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. Springer, Lecture notes in computer science, vol. 7165, pp. 30-42, 3rd International Workshop on Reversible Computation, Gent, Belgium, 04/07/2011. https://doi.org/10.1007/978-3-642-29517-1_3

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AB - We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.

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A reversible processor architecture and its reversible logic design

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