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Optimized reversible binary-coded decimal adders
Michael Kirkedal Thomsen
,
Robert Glück
Datalogisk Institut
43
Citationer (Scopus)
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Keyphrases
Binary Coded Decimal Adder
100%
Decimals
100%
Full Adder
100%
Garbage Bits
50%
Reversible Logic Synthesis
50%
Half Adder
50%
Binary Coded Decimal
50%
Reversible Logic Circuit
50%
CMOS Gate
25%
Circuit Cost
25%
Complete Set
25%
Special Design
25%
Circuit Component
25%
Binary number
25%
Number of Bits
25%
Synthesis Algorithm
25%
Special Purpose
25%
Circuit Delay
25%
System Architecture
25%
Low Power
25%
Reversible Adder
25%
Original Design
25%
Parallel Adder
25%
Reversible Logic Design
25%
Adder Circuits
25%
Computer Science
Binary Coded Decimal
100%
Half Adder
50%
Logic Synthesis
50%
Logic Design
25%
Special Purpose
25%
Synthesis Algorithm
25%
System Architecture
25%
Reversible Power
25%