Garbage-Free Reversible Multiplication and Division

Torben Ægidius Mogensen

doi:10.1007/978-3-319-99498-7_18

Garbage-Free Reversible Multiplication and Division

1 Citationer (Scopus)

Abstract

We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where 0 ≤ B < 2^m and 0 ≤ R < A < 2n, the circuit outputs A and P = A· B + R. Applied in reverse, the circuit takes as input A and P, where 0 < A < 2ⁿ and 0 ≤ P < 2^mA, and outputs A, B = P/A and R = P%A. The circuit uses a total of two ancilla bits. The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O(m×n) gate delay, but this can be improved to O(m×log(n)) by using a modified carry-lookahead adder and an O(log(n)) comparator, both of which are described in the paper. The cost of reducing the gate delay to O(m×log(n)) is O(n) added ancilla bits and a larger gate count.

Originalsprog	Engelsk
Titel	Reversible Computetion : 10th International Conference, RC 2018 Leicester, UK, September 12–14, 2018 Proceedings
Redaktører	Jarkko Kari, Irek Ulidowski
Forlag	Springer
Publikationsdato	22 aug. 2018
Sider	253-268
ISBN (Trykt)	978-3-319-99497-0
ISBN (Elektronisk)	978-3-319-99498-7
DOI	https://doi.org/10.1007/978-3-319-99498-7_18
Status	Udgivet - 22 aug. 2018
Begivenhed	10th International Conference on Reversible Computation, RC 2018 - Leicester, Storbritannien Varighed: 12 sep. 2018 → 14 sep. 2018

Konference

Konference	10th International Conference on Reversible Computation, RC 2018
Land/Område	Storbritannien
By	Leicester
Periode	12/09/2018 → 14/09/2018

Navn	Lecture Notes in Computer Science
Vol/bind	11106
ISSN	0302-9743

Adgang til dokumentet

10.1007/978-3-319-99498-7_18

Citationsformater

Garbage-Free Reversible Multiplication and Division. / Mogensen, Torben Ægidius.

Reversible Computetion: 10th International Conference, RC 2018 Leicester, UK, September 12–14, 2018 Proceedings. red. / Jarkko Kari; Irek Ulidowski. Springer, 2018. s. 253-268 (Lecture Notes in Computer Science, Bind 11106).

Publikation: Bidrag til bog/antologi/rapport › Konferencebidrag i proceedings › Forskning › peer review

Mogensen, TÆ 2018, Garbage-Free Reversible Multiplication and Division. i J Kari & I Ulidowski (red), Reversible Computetion: 10th International Conference, RC 2018 Leicester, UK, September 12–14, 2018 Proceedings. Springer, Lecture Notes in Computer Science, bind 11106, s. 253-268, 10th International Conference on Reversible Computation, RC 2018, Leicester, Storbritannien, 12/09/2018. https://doi.org/10.1007/978-3-319-99498-7_18

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title = "Garbage-Free Reversible Multiplication and Division",

abstract = "We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where 0 ≤ B < 2m and 0 ≤ R < A < 2n, the circuit outputs A and P = A· B + R. Applied in reverse, the circuit takes as input A and P, where 0 < A < 2n and 0 ≤ P < 2mA, and outputs A, B = P/A and R = P%A. The circuit uses a total of two ancilla bits. The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O(m×n) gate delay, but this can be improved to O(m×log(n)) by using a modified carry-lookahead adder and an O(log(n)) comparator, both of which are described in the paper. The cost of reducing the gate delay to O(m×log(n)) is O(n) added ancilla bits and a larger gate count.",

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N2 - We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where 0 ≤ B < 2m and 0 ≤ R < A < 2n, the circuit outputs A and P = A· B + R. Applied in reverse, the circuit takes as input A and P, where 0 < A < 2n and 0 ≤ P < 2mA, and outputs A, B = P/A and R = P%A. The circuit uses a total of two ancilla bits. The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O(m×n) gate delay, but this can be improved to O(m×log(n)) by using a modified carry-lookahead adder and an O(log(n)) comparator, both of which are described in the paper. The cost of reducing the gate delay to O(m×log(n)) is O(n) added ancilla bits and a larger gate count.

AB - We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where We present a circuit design for garbage-free reversible multiplier. Given inputs A, B and R, where 0 ≤ B < 2m and 0 ≤ R < A < 2n, the circuit outputs A and P = A· B + R. Applied in reverse, the circuit takes as input A and P, where 0 < A < 2n and 0 ≤ P < 2mA, and outputs A, B = P/A and R = P%A. The circuit uses a total of two ancilla bits. The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O(m×n) gate delay, but this can be improved to O(m×log(n)) by using a modified carry-lookahead adder and an O(log(n)) comparator, both of which are described in the paper. The cost of reducing the gate delay to O(m×log(n)) is O(n) added ancilla bits and a larger gate count.

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Garbage-Free Reversible Multiplication and Division

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